A publication index.

• Perspective on GaN beyond its commercialized 15–900 V power class, toward both higher-voltage and ultra-low-voltage applications
• Covers digitized RF power amplifiers with hardware–software co-design, GaN CMOS as the missing piece of a full-GaN platform, and cryogenic devices for quantum computing systems
• Analyses gate leakage, buffer leakage and trap dynamics as the reliability limits gating each application

• First experimental study of capacitance, charge and power-switching figures of merit for a large-area vertical GaN power transistor
• 1.2 kV, 5 A FinFET in a 0.45 mm² chip area with 2.1 mΩ·cm² specific on-resistance and 1.3 V threshold voltage
• Extracted switching charges give a practical switching frequency of ~3.5 MHz, against 10–20 kHz for 1.2 kV Si IGBTs
• Switching FOMs exceed commercial 0.9–1.2 kV Si and SiC power transistors

• Review of high-performance vertical GaN transistors and diodes as silicon power devices approach their fundamental limit
• Identifies epitaxial material quality, doping, etch damage and contact formation as the limiting process steps
• Compares lateral and vertical structures for high-power, high-frequency and high-temperature operation

• Argues that wide-bandgap systems are limited not by the switch but by the parasitics of driving it from silicon CMOS control logic
• Surveys monolithic and hybrid CMOS routes across several maturing wide and ultrawide bandgap material platforms
• Frames p-channel device performance as the gating factor for complementary logic in each material system

• Demonstrated a recessed-gate p-channel MISFET on a p-GaN/AlGaN/GaN heterostructure grown on silicon
• A single epi-stack hosts both a 2DEG and a 2DHG, enabling complementary circuit integration on one chip
• Achieved normally-off n-channel operation alongside functional p-type transistors with an ON/OFF ratio ~10⁵

• Monolithically integrated n- and p-channel GaN transistors on a single heterostructure, with no regrowth step required
• Demonstrated a complementary inverter with a record voltage gain of ~27 V/V
• Maintained clean switching characteristics up to 300 °C, proving suitability for high-temperature logic

• Fully vertical GaN-on-Si p-n diode made by selectively removing the Si substrate and buffer, with the cathode formed in backside trenches to an n⁺-GaN layer
• 0.35–0.4 mΩ·cm² specific differential on-resistance (normalized to total device area) with 720 V breakdown
• Baliga figure of merit above 1.5 GW/cm² — a record for vertical GaN power diodes on foreign substrates
• Demonstrates the feasibility of fully vertical GaN devices on low-cost Si rather than bulk GaN

• Demonstrated a self-aligned GaN p-FET process with a 100 nm channel length
• Achieved a record ON-resistance of 400 Ω·mm and ON-current above 5 mA/mm — best-in-class for GaN p-FETs at the time
• Co-integrated with an n-channel p-GaN-gated transistor, validating complementary logic via compact modeling and inverter simulation

• Fully ballistic quantum transport simulation of a GaN nanowire n-MOSFET at Lg = 5 nm
• ION = 1137 µA/µm and Q = gm/SS = 188 µS·decade/µm·mV, evaluated at IOFF = 1 nA/µm and VGS = VDS = VCC = 0.5 V
• ~15% higher ION and ~17% better Q than an equivalent Si nanowire nFET at the same gate length
• Advantage traced to GaN's heavier electron effective mass and lower permittivity at sub-10 nm dimensions

• Demonstrated a self-aligned GaN p-FinFET with I_ON ≈ 140 mA/mm and I_ON/I_OFF > 10⁷ — a record for GaN p-channel devices
• The FinFET geometry compensates for GaN's inherently low hole mobility (~20 cm²/V·s) through superior electrostatic control
• Achieved enhancement-mode operation with a record-low subthreshold swing of 80 mV/dec

• Tungsten replaces the more common molybdenum gate on a MOCVD GaN/AlGaN p-channel heterostructure FET, raising turn-on voltage and cutting gate leakage
• A 500 °C anneal in N₂ heals gate-recess damage and lowers channel resistance
• Scaled devices exceed Imax = 120 mA/mm on GaN-on-Si, against sub-10 mA/mm for most prior GaN p-FET demonstrations
• Long-channel devices (LSD = 5.5 µm, LG = 1.5 µm) benchmarked alongside the scaled geometry

• Fabricated GaN p-MOSFETs with channel lengths scaled down to 200 nm
• Uncovered field-induced acceptor ionization as the key mechanism boosting drive current at short channel lengths
• Achieved a record combination of 45 mA/mm ON-current and a 10⁴ ON-OFF ratio among p-channel GaN devices

• Demonstrated E/D-mode and E/E-mode GaN ring oscillators operational up to 500 °C on a GaN-on-Si platform
• Achieved a propagation delay below 0.18 ns/stage at 25 °C and below 1.48 ns/stage at 500 °C
• Set a new tp vs. LG benchmark for wide-bandgap digital logic at the highest reported operating temperature for a GaN circuit

• N-polar, continuously graded Al0.8Ga0.2N/AlN channel PolFET on SiC, with carriers created by polarization grading rather than impurity doping
• 12 µm source-to-drain device: 62.8 mA/mm maximum drain current with ION/IOFF = 1.1×10⁴
• Drain current stays stable from 20 °C to 250 °C
• Adding a 30 nm Al₂O₃ gate insulator raises maximum drain current to 126 mA/mm

• W/p-GaN-gate AlGaN/GaN HEMT operated for 10 days in a simulated Venus environment: 460 °C, ~92 atm, CO₂/N₂/SO₂ ambient
• In-situ electrical characterization shows proper enhancement-mode operation with <0.09 V threshold voltage variation
• Post-test advanced microscopy links the stress conditions to changes in the epitaxial and device structures
• First demonstration and comprehensive analysis of E-mode GaN transistors under such conditions

• Benchmarked five metal contacts (Ni, Ir, Ru, Mo, W/Au) on p-GaN using a single, uniform epitaxial platform
• Found strong Fermi-level pinning across all metals (pinning factor ~0.15), explaining persistently high contact resistance
• Identified Ru/Au as the standout performer, with an ultra-low contact resistivity of 3.45 × 10⁻⁶ Ω·cm²

• Achieved a record ID,max of −300 mA/mm and RON of 27 Ω·mm for a MOCVD-grown, self-aligned GaN p-channel FinFET with a 20 nm fin width
• Demonstrated a compatible self-aligned n-channel p-GaN-gate FET (ID,max = 525 mA/mm, RON = 2.9 Ω·mm) on the same epitaxial platform
• Established a leading combined p-FET/n-FET performance benchmark for GaN complementary technology on silicon

• TFET modified with a ferroelectric complementary gate dielectric operating in the negative-capacitance regime
• Combines two independent subthreshold-swing reduction mechanisms in one device, beating conventional TFETs on both
• Simple analytical tunnel current model developed and validated for the proposed structure
• Predicts high ON current at low VGS together with a reduced subthreshold swing

• In-situ measurement of E-mode p-GaN-gate AlGaN/GaN HEMTs from room temperature to 500 °C
• Vth, Ron, ID,max and IG,max trends follow first-order changes in semiconductor properties, with no anomalous degradation mechanism
• Fabricated transistors hold stable performance over 20 days at 500 °C
• First systematic high-temperature study of this device class, aimed at mixed-signal and low-voltage power circuits

• Transfer length method measurements in air from 25 to 500 °C compare regrown and alloyed ohmic contacts on AlGaN/GaN-on-Si HEMTs
• Regrown contacts appear stable to 500 °C over ~1 h testing; alloyed contact resistance appears to fall from 300 to 500 °C within widening error bounds
• Both technologies remain stable for at least 48 h at 500 °C, after which rising sheet resistance limits measurement certainty
• Advanced microscopy confirms both contact regions stay structurally intact after prolonged exposure

• E-mode p-GaN-gate AlGaN/GaN HEMT exposed for 11 days to a full simulated Venus environment: 460 °C, 94 bar, CO₂/N₂/SO₂
• Transistor, TLM and Hall-effect measurements versus temperature identify mobility reduction as the primary cause of on-state degradation
• Combines in-situ burn-in electrical measurement with advanced microscopy of structural deformation
• Findings generalize to the design and deployment of III-N devices for harsh environment operation

* Self-aligned p-channel FinFET scaled to 20 nm fin width, achieving ION = −300 mA/mm — a record for MOCVD-grown III-N p-FETs
* Systematic study of fin-width scaling and recess depth on transistor behaviour
* New self-aligned scaled n-channel p-GaN-gate enhancement-mode FET process, compatible with the p-FinFET, on the same platform
* Pushes GaN complementary technology toward circuit-level performance limits on GaN-on-Si

• Demonstrated the first NbN-gated AlGaN/GaN HEMT technology for quantum computing applications, with 250 nm gate lengths
• Achieved excellent gate modulation (ID,ON/ID,OFF ~ 10^8) and current saturation at 4.2 K
• Revealed a low DC power dissipation of 25 μW/μm at the bias point for minimum noise, evaluated alongside RF performance at 4.2 K

• 32-bit ROM, 1-bit 4-transistor SRAM, D latch and D flip-flop demonstrated on a monolithically integrated GaN-on-Si platform using n-FET-only E/D-mode logic
• All memory cells operate stably at 300 °C
• Maximum D flip-flop clock frequency estimated at 36 MHz at 300 °C from measured setup time
• Highest reported operating temperature for GaN memory, opening the way to high-temperature mixed-signal systems

• Single-phase Bi0.8La0.2Fe(1−x)TaxO₃ ceramics (x = 0, 0.01, 0.03, 0.05) synthesized by conventional solid-state reaction, calcined at 800 °C and sintered at 1000 °C for 2 h
• XRD confirms a single-phase distorted R3c structure across all compositions
• Ta's strong pinning effect cuts average grain size from 10.6 µm (undoped) to 0.92 µm at x = 0.05, measured by FESEM
• Ta-doped samples show a room-temperature dielectric constant above 2000

• Atomistic quantum transport simulation of 5 nm gate-length GaN nanowire nFETs across several cross-sectional geometries
• Square cross-sections give over 30% higher drive current than simulated Si nanowire nFETs in both low-standby-power (IOFF = 1 nA/µm) and high-performance (IOFF = 100 nA/µm) corners
• Triangular cross-sections matched to GaN's wurtzite structure reach 62 mV/decade subthreshold swing at Tnw = 2.4 nm
• Same geometry delivers IDSAT > 2×10⁶ µA/µm² with a superior energy–delay product to Si

• Proposed the multimetal gate (MMG) concept — spatially varying the gate work function along the device width
• TCAD-calibrated simulations show 6.3 dB higher OIP3/Pdc and 12.9 dB lower IMD3 versus a baseline HEMT
• Delivered simultaneous gains in linearity, output power (6.91 W/mm), and efficiency (65% PAE)

• CAD framework for high-temperature GaN-on-Si established and experimentally validated up to 500 °C — the highest temperature reached by such a framework for GaN
• Key functional building blocks including an arithmetic logic unit demonstrated at 300 °C
• Transistor compact models calibrated to 500 °C, the highest temperature modelled for an enhancement-mode GaN transistor
• Simulated and measured circuits agree within <0.1 V of voltage swing, with dynamic timing trends accurately captured

• Evaluated GaN CMOS inverters built from self-aligned p-FETs and n-FinFETs, achieving 1.4 V low and 2.8 V high noise margins at VDD = 5 V
• Simulated a 6-T SRAM cell, extracting write and hold margins at both 25 °C and 300 °C
• Confirmed negligible performance degradation of GaN CMOS logic building blocks at high temperature (300 °C)

• Proposes the Negative Capacitance Single Gate SOI TFET (NC-SG-SOI-TFET) with a full analytical model
• Channel potential and electric field obtained by solving the Poisson equation; drain current from the band-to-band generation rate
• Ferroelectric oxide layer incorporated through one-dimensional Landau formalism
• Predicts 11.82 mV/decade subthreshold swing at 0.65 V operating voltage for 10⁻⁸ A drain current, with reduced short-channel effects versus conventional TFETs
  

• Summarizes recent progress on high-frequency GaN power switches, covering both lateral and vertical device structures
• Presents an all-GaN complementary gate driver technology that could push GaN power circuit operating frequency beyond 10 MHz
• Closes on future directions including superjunction structures for further device performance gains

• Combined Schottky-emission and space-charge-limited-current (SCLC) models to explain p-GaN conduction across bias and temperature
• Pinpointed trap states in the p-GaN channel as a key factor governing high-temperature current transport
• Provided design insight for GaN electronics destined for harsh environments — from downhole drilling to planetary probes

• Achieved a 10.7 dB improvement in OIP3/PDC by using a multimetal gate scheme to suppress third-order transconductance (gm3)
• Delivered a 6× higher 1-dB compression point (3.60 vs. 0.60 W/mm) compared to a conventional HEMT
• Validated under real 5G FR1 signal conditions — ACPR held below –40 dBc with a 2.6% reduction in EVM

• Transforms geometrically complex 2D field plate structures into a concise feature space, sharply reducing the training data requirement
• Machine learning-assisted framework both optimizes field plate geometry and performs inverse design
• Addresses a gap in ML for GaN devices, where field plate structures had been largely untouched because of their geometric complexity
• Method is not GaN-specific and extends to other device families

• Short survey of recent 2D and 3D GaN device developments and the metrics they improve: efficiency, fT, linearity, power density and switching speed
• Mostly RF cases, with one power electronics example and one GaN integrated circuit example

• C–V characteristics and direct-tunneling gate leakage of antimonide surface-channel MOSFETs computed by self-consistently solving the coupled Schrödinger–Poisson equations
• Wave function penetration and strain effects both included in the solution
• Sensitivity mapped against oxide thickness, channel composition, channel thickness and temperature for the n-channel device
• Fills a gap where experimental p-channel I–V and gate leakage data existed but no self-consistent C–V simulation had been reported
  

• Built an ANN model (R² = 99%, <1% error) that predicts HEMT structural parameters directly from target breakdown voltage and leakage specs
• Coupled the ANN with a genetic algorithm to identify Pareto-optimal field-plate designs, validated against TCAD (1.67% error)
• Introduced a fast, field-based method to predict current collapse — bypassing slow pulsed-DC characterization

• Built the first experimentally calibrated TCAD models explaining optically triggered (OT) GaN transistor physics
• Optimized barrier thickness, Al composition, and back-barrier design to achieve an 8× faster response time
• Extended the optimization to a vertical GaN FinFET, boosting ON-OFF ratio while suppressing persistent photocurrent

• Tests whether the multimetal gate scheme still suppresses gm3 once Fermi-level pinning erodes the effective work-function difference between gate metals
• TCAD, compact modeling and load-pull simulation show gm3 suppression and improved IMD3 survive the pinning
• OIP3/Pdc of 18.9 dB at an FLP factor of 0.43 — 10.7 dB above the conventional planar HEMT
• Output power back-off comparison across FLP factors establishes the MMG architecture as practically robust

• By 2030 roughly 80% of all US electricity is expected to flow through power electronics, demanding far higher efficiency and smaller form factor than silicon systems deliver
• Argues III-nitride and other ultra-wide bandgap materials are the natural platform, combining excellent transport with high critical electric field
• Reviews group progress on high-voltage wide bandgap power transistors and diodes

• 100–400 nm fins defined under the gate electrode of AlGaN/GaN transistors raise gate modulation efficiency and allow threshold voltage tuning
• Proper fin design improves DC performance and significantly enhances RF linearity
• Benchmarks the theoretical performance of GaN channels scaled below 5 nm against competing technologies, drawing on GaN's wide bandgap, large effective mass and moderate permittivity
  

• Demonstrated an all-GaN operational amplifier combining enhancement- and depletion-mode HEMTs, operable up to 500 °C
• Achieved 88 dB DC gain and 75 MHz unity-gain frequency at room temperature, retaining 61 dB gain and 8.4 MHz UGF at 500 °C
• Benchmarked against state-of-the-art Si, SiC, and GaN op-amp designs across both room and high-temperature operation

• Identified Mg-related hole traps (110 meV activation energy) as the dominant factor limiting hole transport in bulk p-GaN
• Showed that sheet resistance follows a Poole–Frenkel field dependence, explaining why conduction changes with bias
• Revealed Schottky barrier lowering via thermionic field emission at the Ru/p-GaN contact — a key input for contact design

• Compact, low-reflection 2.45 GHz waveguide structure based on a 3-dB waveguide bridge for high-power microwave plasma
• Redirects reflected power to a matched load, eliminating conventional circulators and multistub tuners while keeping source-port reflection minimal
• Finite-element simulation optimizes waveguide dimensions, electric field distribution and VSWR under dielectric loading; dominant TE mode, cutoff frequency and guided wavelength verified analytically
• Optimized structure achieves simulated VSWR below 1.5; a fabricated prototype sustains stable plasma generation
  

• Enabled optical triggering at longer wavelengths (≥395 nm) for the first time, overcoming the limits of conventional UV-triggered GaN switches
• Proposed a novel p-InGaN/p-GaN/AlGaN/GaN gate stack, reaching a responsivity of 6.7 × 10³ A/W
• Cut fall time by 5.75× relative to conventional optically triggered transistor designs

• Modulates AlGaN barrier thickness under the gate along its width, creating a local equivalent threshold voltage offset so the device behaves as parallel transistors with staggered Vth
• Resulting gm3 cancellation suppresses the gm3 peak tenfold versus conventional planar-gated AlGaN/GaN HEMTs, and linearizes the Cgs–VGS curve
• Compact modeling and large-signal simulation give a 7 dB improvement in OIP3/PDC at 5 GHz
• Around 10 dB suppression of two-tone third-order intermodulation distortion

• Physically based analytical compact model for quantized eigen energies and wave functions, including the penetration effect
• Applies to the quantum well structures common in modern nanoscale devices, in both silicon and III-V material systems
• Predicts all eigen energies accurately without any fitting parameters, unlike existing models in the literature
• Validated against numerical simulation with significantly better agreement than available methods

• Complete C–V characterization of the InAsySb1−y QWFET plus ballistic transport analysis
• 1-D coupled Schrödinger–Poisson equations solved with wave function penetration and strain effects included
• Dependence studied against oxide thickness, channel composition, top barrier composition, channel thickness and temperature
• Capacitance rises rapidly before the cross-over point then saturates, tracking the sheet charge density slope; trends match an experimentally grown reference device

• C–V and ballistic I–V characteristics of sub-35 nm double-gate SOI Flexible-FETs obtained self-consistently with a coupled Schrödinger–Poisson solver, including quantum mechanical effects
• Depletion-to-accumulation transition (threshold) of the C–V curve shifts positive under negative bottom-gate bias, confirming the device's control mechanism
• Ballistic performance also studied against bottom-gate bias variation
• First reported self-consistent C–V and ballistic I–V characterization for this device, complementing prior ATLAS short-channel studies
  

• Self-consistent C–V characterization of a depletion-mode buried-channel InGaAs/InAs quantum well FET with quantum mechanical effects included
• Studied against three process parameters: indium composition, gate dielectric and oxide thickness
• Higher indium content in the InGaAs barrier raises both inversion capacitance and ballistic current
• Completes the electrostatic picture for depletion-type buried-channel QWFETs, previously reported only for enhancement-type devices
  

• Explicit analytical expression for top-gate threshold voltage versus JFET bottom-gate voltage, derived from the 2-D Poisson equation with Young's parabolic approximation
• Model matches experimental results for both 180 nm n-channel and p-channel Flexible-FETs
• Threshold voltage trends against oxide thickness, silicon channel thickness and doping concentration agree qualitatively with SILVACO simulations