Publications

A publication index.

Journal

GaN Goes Analog: A 500 °C-Ready Operational Amplifier

A gallium nitride-based operational amplifier for high temperature applications

P. Mahmud, Q. Xie, M. Yuan, T. Palacios, N. Chowdhury

Semiconductor Science and Technology · 10.1088/1361-6641/ae0e44

Demonstrated an all-GaN operational amplifier combining enhancement- and depletion-mode HEMTs, operable up to 500 °C
Achieved 88 dB DC gain and 75 MHz unity-gain frequency at room temperature, retaining 61 dB gain and 8.4 MHz UGF at 500 °C
Benchmarked against state-of-the-art Si, SiC, and GaN op-amp designs across both room and high-temperature operation

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Schematic of the four-stage GaN operational amplifier combining E-mode and D-mode HEMTs.

Journal

A New Gate Architecture for Linear GaN Power Amplifiers

AlGaN/GaN-Based Multimetal Gated High-Electron-Mobility Transistor With Improved Linearity

Md. Tasnim Azad, Toiyob Hossain, Bejoy Sikder, Qingyun Xie, Mengyang Yuan, Eiji Yagyu, Koon Hoo Teo, Tomás Palacios, Nadim Chowdhury

IEEE Transactions on Electron Devices · 10.1109/ted.2023.3311422

Proposed the multimetal gate (MMG) concept — spatially varying the gate work function along the device width
TCAD-calibrated simulations show 6.3 dB higher OIP3/Pdc and 12.9 dB lower IMD3 versus a baseline HEMT
Delivered simultaneous gains in linearity, output power (6.91 W/mm), and efficiency (65% PAE)

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3D schematic of the multimetal-gated AlGaN/GaN HEMT with key structural parameters for improved linearity.

Journal

Cracking the Contact Problem: Fermi-Level Pinning on p-Type GaN

Barrier heights and Fermi level pinning in metal contacts on p-type GaN

Sumaiya Wahid, Nadim Chowdhury, Md. Kawsar Alam, Tomás Palacios

Applied Physics Letters · 10.1063/5.0010699

Benchmarked five metal contacts (Ni, Ir, Ru, Mo, W/Au) on p-GaN using a single, uniform epitaxial platform
Found strong Fermi-level pinning across all metals (pinning factor ~0.15), explaining persistently high contact resistance
Identified Ru/Au as the standout performer, with an ultra-low contact resistivity of 3.45 × 10⁻⁶ Ω·cm²

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Current–voltage characteristics of five bilayer metal contacts on p-GaN used to extract Fermi-level pinning and contact resistivity.

Conference

Scaling Down GaN p-MOSFETs: The Physics Behind Better Performance

Field-induced Acceptor Ionization in Enhancement-mode GaN p-MOSFETs

Nadim Chowdhury, Qingyun Xie, John Niroula, Nitul S. Rajput, Kai Cheng, Han Wui Then, Tomás Palacios

IEDM · 10.1109/iedm13553.2020.9371963

Fabricated GaN p-MOSFETs with channel lengths scaled down to 200 nm
Uncovered field-induced acceptor ionization as the key mechanism boosting drive current at short channel lengths
Achieved a record combination of 45 mA/mm ON-current and a 10⁴ ON-OFF ratio among p-channel GaN devices

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Contact and sheet resistance vs. bias, and 3D schematic of the self-aligned GaN p-MOSFET gate stack.

Conference

The First Self-Aligned GaN p-FET: A Building Block for Complementary GaN

First Demonstration of a Self-Aligned GaN p-FET

Nadim Chowdhury, Qingyun Xie, Mengyang Yuan, Nitul S. Rajput, Xiang Peng, Kai Cheng, Han Wui Then, Tomás Palacios

IEDM · 10.1109/iedm19573.2019.8993569

Demonstrated a self-aligned GaN p-FET process with a 100 nm channel length
Achieved a record ON-resistance of 400 Ω·mm and ON-current above 5 mA/mm — best-in-class for GaN p-FETs at the time
Co-integrated with an n-channel p-GaN-gated transistor, validating complementary logic via compact modeling and inverter simulation

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STEM image and schematic of the self-aligned GaN p-FET with a 100 nm channel length.

Conference

GaN Meets Quantum: Cryogenic Transistors for Qubit Readout

Q. Xie, N. Chowdhury, A. Zubair, M. Sánchez Lozano, J. Lemettinen, M. Colangelo, O. Medeiros, I. Charaev, K. K. Berggren, P. Gumann, D. Pfeiffer, T. Palacios

Symposium on VLSI Technology, 2021

Demonstrated the first NbN-gated AlGaN/GaN HEMT technology for quantum computing applications, with 250 nm gate lengths
Achieved excellent gate modulation (ID,ON/ID,OFF ~ 10^8) and current saturation at 4.2 K
Revealed a low DC power dissipation of 25 μW/μm at the bias point for minimum noise, evaluated alongside RF performance at 4.2 K

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Proposed use of the NbN-gated GaN HEMT as a cryogenic LNA for qubit readout.

Journal

GaN Logic That Keeps Ticking at 500 °C: Ring Oscillators for Extreme Environments

GaN Ring Oscillators Operational at 500 °C Based on a GaN-on-Si Platform

M. Yuan, Q. Xie, K. Fu, T. Hossain, J. Niroula, J. A. Greer, N. Chowdhury, Y. Zhao, T. Palacios

IEEE Electron Device Letters · 10.1109/LED.2022.3204566

Demonstrated E/D-mode and E/E-mode GaN ring oscillators operational up to 500 °C on a GaN-on-Si platform
Achieved a propagation delay below 0.18 ns/stage at 25 °C and below 1.48 ns/stage at 500 °C
Set a new tp vs. LG benchmark for wide-bandgap digital logic at the highest reported operating temperature for a GaN circuit

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GaN ring oscillator micrograph and output waveforms across temperatures up to 500 °C.

Conference

Switching GaN with Light: A New Gate Stack for Optical Triggering

Gate Stack Engineering and Carrier Dynamics of Optically Triggered GaN Transistors on 650V GaN-on-Si Power Platform

Rafid Hassan Palash, Jung-Han Hsia, Soumik Saha, Nittya Ananda Biswas, Qingyun Xie, Victor Moroz, Tomás Palacios, Nadim Chowdhury

IEDM · 10.1109/IEDM50572.2025.11353658

Enabled optical triggering at longer wavelengths (≥395 nm) for the first time, overcoming the limits of conventional UV-triggered GaN switches
Proposed a novel p-InGaN/p-GaN/AlGaN/GaN gate stack, reaching a responsivity of 6.7 × 10³ A/W
Cut fall time by 5.75× relative to conventional optically triggered transistor designs

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Device schematics and TCAD calibration of the lateral p-GaN gate optically triggered HEMT, showing measured vs. simulated I–V, intensity, and transient response.

Journal

Pushing GaN CMOS to the Limit: Highly Scaled Complementary Transistors on Silicon

Highly Scaled GaN Complementary Technology on a Silicon Substrate

Q. Xie, M. Yuan, B. Sikder, J. Niroula, J. A. Greer, N. S. Rajput, N. Chowdhury, T. Palacios

IEEE Transactions on Electron Devices · 10.1109/TED.2023.3247684

Achieved a record ID,max of −300 mA/mm and RON of 27 Ω·mm for a MOCVD-grown, self-aligned GaN p-channel FinFET with a 20 nm fin width
Demonstrated a compatible self-aligned n-channel p-GaN-gate FET (ID,max = 525 mA/mm, RON = 2.9 Ω·mm) on the same epitaxial platform
Established a leading combined p-FET/n-FET performance benchmark for GaN complementary technology on silicon

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Epitaxial structure of the scaled GaN p-FinFET and n-FET on the same platform.

Journal

Beyond Room Temperature: Hole Transport Physics in p-GaN Heterostructures

Hole transport mechanism at high temperatures in p-GaN/AlGaN/GaN heterostructure

Bejoy Sikder, Toiyob Hossain, Qingyun Xie, John Niroula, Nitul S. Rajput, Koon Hoo Teo, Hiroshi Amano, Tomás Palacios, Nadim Chowdhury

Applied Physics Letters · 10.1063/5.0203344

Combined Schottky-emission and space-charge-limited-current (SCLC) models to explain p-GaN conduction across bias and temperature
Pinpointed trap states in the p-GaN channel as a key factor governing high-temperature current transport
Provided design insight for GaN electronics destined for harsh environments — from downhole drilling to planetary probes

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TEM cross-section of the Ru/p-GaN contact after annealing at 500 °C, showing the metal–semiconductor interface at increasing magnification.

Journal

Machine Learning Meets GaN: Inverse-Designing RF Power Transistors

Inverse Design of AlGaN/GaN HEMT RF Device with Source Connected Field Plate

A Das, Saimur Rahman Arnab, Xiaofeng Xiang, Rafid Hassan Palash, Toiyob Hossain, Bejoy Sikder, Eiji Yagyu, Marika Nakamura, Koon Hoo Teo, Nadim Chowdhury

Advanced Theory and Simulations · 10.1002/adts.202401207

Built an ANN model (R² = 99%, <1% error) that predicts HEMT structural parameters directly from target breakdown voltage and leakage specs
Coupled the ANN with a genetic algorithm to identify Pareto-optimal field-plate designs, validated against TCAD (1.67% error)
Introduced a fast, field-based method to predict current collapse — bypassing slow pulsed-DC characterization

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Simulated electric-field maps across field-plate variations and the ANN architecture used for inverse design of the AlGaN/GaN HEMT.

Conference

Benchmarking GaN CMOS: From Inverters to SRAM at High Temperature

Performance Estimation of GaN CMOS Technology

N. Chowdhury, J. Jung, Q. Xie, M. Yuan, K. Cheng, T. Palacios

Device Research Conference (DRC), 2021

Evaluated GaN CMOS inverters built from self-aligned p-FETs and n-FinFETs, achieving 1.4 V low and 2.8 V high noise margins at VDD = 5 V
Simulated a 6-T SRAM cell, extracting write and hold margins at both 25 °C and 300 °C
Confirmed negligible performance degradation of GaN CMOS logic building blocks at high temperature (300 °C)

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Simulated 6-T SRAM write, hold, and read butterfly curves at 25 °C and 300 °C, with inscribed noise-margin squares shrinking at high temperature.

Conference

Fine-Tuning Light-Activated GaN Transistors for Faster, Cleaner Switching

Performance Optimization of GaN Based Optically Triggered Transistors

Rafid Hassan Palash, Toiyob Hossain, Bejoy Sikder, Qingyun Xie, Victor Moroz, Tomás Palacios, Nadim Chowdhury

IEDM · 10.1109/iedm50854.2024.10873587

Built the first experimentally calibrated TCAD models explaining optically triggered (OT) GaN transistor physics
Optimized barrier thickness, Al composition, and back-barrier design to achieve an 8× faster response time
Extended the optimization to a vertical GaN FinFET, boosting ON-OFF ratio while suppressing persistent photocurrent

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Fabricated device layout, epitaxial structure, TCAD calibration workflow, and measured vs. simulated I–V and transient response of the optically triggered GaN transistor.

Journal

Toward GaN CMOS: The First Regrowth-Free Complementary Logic on Silicon

Regrowth-Free GaN-Based Complementary Logic on a Si Substrate

Nadim Chowdhury, Qingyun Xie, Mengyang Yuan, Kai Cheng, Han Wui Then, Tomás Palacios

IEEE Electron Device Letters · 10.1109/led.2020.2987003

Monolithically integrated n- and p-channel GaN transistors on a single heterostructure, with no regrowth step required
Demonstrated a complementary inverter with a record voltage gain of ~27 V/V
Maintained clean switching characteristics up to 300 °C, proving suitability for high-temperature logic

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Epitaxial structure, TEM image, and fabricated inverter chip for the regrowth-free GaN complementary logic platform.

Journal

Decoding Hole Traps in p-GaN: A Path to Better GaN CMOS

Role of Mg hole traps in hole transport of p-GaN/UID-GaN/AlGaN/GaN heterostructure

Tanvir Hossain, A. K. M. Anindya Alam, Qingyun Xie, Hiroshi Amano, Tomás Palacios, Nadim Chowdhury

Applied Physics Letters · 10.1063/5.0333494

Identified Mg-related hole traps (110 meV activation energy) as the dominant factor limiting hole transport in bulk p-GaN
Showed that sheet resistance follows a Poole–Frenkel field dependence, explaining why conduction changes with bias
Revealed Schottky barrier lowering via thermionic field emission at the Ru/p-GaN contact — a key input for contact design

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Epitaxial schematic of the p-GaN/UID-GaN/AlGaN/GaN heterostructure with Ru source and drain contacts used for temperature-dependent hole transport analysis.

Journal

A Milestone for GaN CMOS: The First High-Performance p-Channel FinFET

Self-Aligned E-Mode GaN p-Channel FinFET With ION > 100 mA/mm and ION/IOFF > 10⁷

Nadim Chowdhury, Qingyun Xie, Tomás Palacios

IEEE Electron Device Letters · 10.1109/led.2022.3140281

Demonstrated a self-aligned GaN p-FinFET with I_ON ≈ 140 mA/mm and I_ON/I_OFF > 10⁷ — a record for GaN p-channel devices
The FinFET geometry compensates for GaN's inherently low hole mobility (~20 cm²/V·s) through superior electrostatic control
Achieved enhancement-mode operation with a record-low subthreshold swing of 80 mV/dec

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SEM cross-section of the fabricated self-aligned GaN p-channel FinFET.

Journal

Engineering Linearity: Multimetal Gates for Cleaner 5G Power Amplifiers

System-Technology Co-Optimization of Multimetal Gated AlGaN/GaN HEMT for Improved RF Linearity

Toiyob Hossain, Tanvir Hossain, A. K. M. Anindya Alam, Bejoy Sikder, Qingyun Xie, Mengyang Yuan, Eiji Yagyu, Koon Hoo Teo, Tomás Palacios, Nadim Chowdhury

IEEE Journal of the Electron Devices Society · 10.1109/jeds.2024.3506618

Achieved a 10.7 dB improvement in OIP3/PDC by using a multimetal gate scheme to suppress third-order transconductance (gm3)
Delivered a 6× higher 1-dB compression point (3.60 vs. 0.60 W/mm) compared to a conventional HEMT
Validated under real 5G FR1 signal conditions — ACPR held below –40 dBc with a 2.6% reduction in EVM

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Multimetal gate schematic and ACPR/EVM performance of the MMG HEMT under 16- and 64-QAM 5G FR1 signals.

Journal

Laying the Foundation: The First p-Channel GaN Transistor on Silicon

p-Channel GaN Transistor Based on p-GaN/AlGaN/GaN on Si

Nadim Chowdhury, Jori Lemettinen, Qingyun Xie, Yuhao Zhang, Nitul S. Rajput, Xiang Peng, Kai Cheng, Sami Suihkonen, Han Wui Then, Tomás Palacios

IEEE Electron Device Letters · 10.1109/led.2019.2916253

Demonstrated a recessed-gate p-channel MISFET on a p-GaN/AlGaN/GaN heterostructure grown on silicon
A single epi-stack hosts both a 2DEG and a 2DHG, enabling complementary circuit integration on one chip
Achieved normally-off n-channel operation alongside functional p-type transistors with an ON/OFF ratio ~10⁵

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Fabrication process flow and top-view of the recessed-gate p-channel GaN transistor on Si.

Journal

From Power Bricks to Qubits: Where GaN Goes Next

Emerging GaN Technologies for Power, RF, Digital, and Quantum Computing Applications: Recent Advances and Prospects

K. H. Teo, Y. Zhang, N. Chowdhury, S. Rakheja, R. Ma, Q. Xie, E. Yagyu, K. Yamanaka, K. Li, T. Palacios

Journal of Applied Physics · 10.1063/5.0061555

Perspective on GaN beyond its commercialized 15–900 V power class, toward both higher-voltage and ultra-low-voltage applications
Covers digitized RF power amplifiers with hardware–software co-design, GaN CMOS as the missing piece of a full-GaN platform, and cryogenic devices for quantum computing systems
Analyses gate leakage, buffer leakage and trap dynamics as the reliability limits gating each application

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Journal

Sixty Labs, One Map: The Blueprint That Set GaN's Course

The 2018 GaN Power Electronics Roadmap

H. Amano, Y. Baines, E. Beam, M. Borga, T. Bouchet, P. R. Chalker, M. Charles, K. J. Chen, N. Chowdhury

Journal of Physics D: Applied Physics · 10.1088/1361-6463/aaaf9d

Community roadmap compiled from ~60 contributing authors across the leading GaN groups worldwide, spanning 49 journal pages
Covers epitaxial lift-off and growth on large-area substrates, lateral and vertical device architectures, reliability, and system-level integration
Reports 200 mm GaN processed in a standard CMOS fab with dynamic Ron dispersion below 20% up to 650 V across 25–150 °C

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Journal

A 1.2 kV Switch That Runs at Megahertz

Large-Area 1.2-kV GaN Vertical Power FinFETs With a Record Switching Figure of Merit

Y. Zhang, M. Sun, J. Perozek, Z. Liu, A. Zubair, D. Piedra, N. Chowdhury, X. Gao, K. Shepard, T. Palacios

IEEE Electron Device Letters · 10.1109/LED.2018.2880306

First experimental study of capacitance, charge and power-switching figures of merit for a large-area vertical GaN power transistor
1.2 kV, 5 A FinFET in a 0.45 mm² chip area with 2.1 mΩ·cm² specific on-resistance and 1.3 V threshold voltage
Extracted switching charges give a practical switching frequency of ~3.5 MHz, against 10–20 kHz for 1.2 kV Si IGBTs
Switching FOMs exceed commercial 0.9–1.2 kV Si and SiC power transistors

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Journal

Growing Upward: The Material Problems Vertical GaN Must Solve

Materials and Processing Issues in Vertical GaN Power Electronics

J. Hu, Y. Zhang, M. Sun, D. Piedra, N. Chowdhury, T. Palacios

Materials Science in Semiconductor Processing

Review of high-performance vertical GaN transistors and diodes as silicon power devices approach their fundamental limit
Identifies epitaxial material quality, doping, etch damage and contact formation as the limiting process steps
Compares lateral and vertical structures for high-power, high-frequency and high-temperature operation

Journal

Can a Wide Bandgap Ever Do CMOS?

Prospects for Wide Bandgap and Ultrawide Bandgap CMOS Devices

S. J. Bader, H. Lee, R. Chaudhuri, S. Huang, A. Hickman, A. Molnar, H. G. Xing, D. Jena, H. W. Then, N. Chowdhury, T. Palacios

IEEE Transactions on Electron Devices

Argues that wide-bandgap systems are limited not by the switch but by the parasitics of driving it from silicon CMOS control logic
Surveys monolithic and hybrid CMOS routes across several maturing wide and ultrawide bandgap material platforms
Frames p-channel device performance as the gating factor for complementary logic in each material system

Journal

The Missing Half of GaN: A Working p-Channel Transistor on Silicon

p-Channel GaN Transistor Based on p-GaN/AlGaN/GaN on Si

N. Chowdhury, J. Lemettinen, Q. Xie, Y. Zhang, N. S. Rajput, P. Xiang, K. Cheng, S. Suihkonen, H. W. Then, T. Palacios

IEEE Electron Device Letters · 10.1109/LED.2019.2916253

Recessed-gate p-channel MISFET on MOCVD-grown p-GaN (70 nm)/Al0.2Ga0.8N (15 nm)/GaN on a Si substrate
Epitaxy hosts both a 2DEG and a 2DHG, and the p-GaN cap depletes the 2DEG to give normally-off n-channel devices on the same wafer
Long-channel p-FETs show ~10⁵ on–off current ratio with low on-resistance at the measured bias

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Journal

GaN CMOS Without a Single Regrowth Step

Regrowth-Free GaN-Based Complementary Logic on a Si Substrate

N. Chowdhury, Q. Xie, M. Yuan, K. Cheng, H. W. Then, T. Palacios

IEEE Electron Device Letters · 10.1109/LED.2020.2987003

n- and p-channel GaN FETs monolithically integrated on one GaN/AlGaN/GaN double heterostructure with no epitaxial regrowth
n-FET: enhancement mode, Vth ≈ 0.2 V, on–off ratio 10⁷, Ron = 6 Ω·mm. p-FET: enhancement mode, Vth = −1 V, on–off ratio 10⁴, Ron = 2.3 kΩ·mm
Complementary inverter reaches a record maximum voltage gain of ~27 V/V at VDD = 5 V, with the peak at 0.59 V input
Excellent transfer characteristics retained up to 300 °C operation

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Journal

Cutting the Silicon Away to Let GaN Conduct Vertically

720-V/0.35-mΩ·cm² Fully Vertical GaN-on-Si Power Diodes by Selective Removal of Si Substrates and Buffer Layers

Y. Zhang, M. Yuan, N. Chowdhury, K. Cheng, T. Palacios

IEEE Electron Device Letters · 10.1109/LED.2018.2819642

Fully vertical GaN-on-Si p-n diode made by selectively removing the Si substrate and buffer, with the cathode formed in backside trenches to an n⁺-GaN layer
0.35–0.4 mΩ·cm² specific differential on-resistance (normalized to total device area) with 720 V breakdown
Baliga figure of merit above 1.5 GW/cm² — a record for vertical GaN power diodes on foreign substrates
Demonstrates the feasibility of fully vertical GaN devices on low-cost Si rather than bulk GaN

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Conference

Self-Alignment Comes to the GaN p-FET

First Demonstration of a Self-Aligned GaN p-FET

N. Chowdhury, Q. Xie, M. Yuan, N. S. Rajput, P. Xiang, K. Cheng, H. W. Then, T. Palacios

2019 IEEE International Electron Devices Meeting (IEDM) · 10.1109/IEDM19573.2019.8993569

First self-aligned GaN p-FET, on a GaN/Al0.2Ga0.8N (20 nm)/GaN heterostructure grown by MOCVD on a Si substrate
100 nm channel with 70 nm recess depth: record 400 Ω·mm on-resistance and >5 mA/mm on-current with 6×10⁵ on–off ratio
Enhancement-mode operation with Vth = −1 V, making it viable for Si-integrable GaN complementary circuits
A monolithically integrated p-GaN-gate n-channel transistor plus compact modeling and inverter simulation complete the platform

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Journal

A GaN Transistor With a Five-Nanometre Channel

N. Chowdhury, G. Iannaccone, G. Fiori, D. A. Antoniadis, T. Palacios

IEEE Electron Device Letters

Fully ballistic quantum transport simulation of a GaN nanowire n-MOSFET at Lg = 5 nm
ION = 1137 µA/µm and Q = gm/SS = 188 µS·decade/µm·mV, evaluated at IOFF = 1 nA/µm and VGS = VDS = VCC = 0.5 V
~15% higher ION and ~17% better Q than an equivalent Si nanowire nFET at the same gate length
Advantage traced to GaN's heavier electron effective mass and lower permittivity at sub-10 nm dimensions