Publications

A publication index.

Journal

Laying the Foundation: The First p-Channel GaN Transistor on Silicon

p-Channel GaN Transistor Based on p-GaN/AlGaN/GaN on Si

Nadim Chowdhury, Jori Lemettinen, Qingyun Xie, Yuhao Zhang, Nitul S. Rajput, Xiang Peng, Kai Cheng, Sami Suihkonen, Han Wui Then, Tomás Palacios

IEEE Electron Device Letters · 10.1109/led.2019.2916253

Demonstrated a recessed-gate p-channel MISFET on a p-GaN/AlGaN/GaN heterostructure grown on silicon
A single epi-stack hosts both a 2DEG and a 2DHG, enabling complementary circuit integration on one chip
Achieved normally-off n-channel operation alongside functional p-type transistors with an ON/OFF ratio ~10⁵

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Fabrication process flow and top-view of the recessed-gate p-channel GaN transistor on Si.

Journal

Toward GaN CMOS: The First Regrowth-Free Complementary Logic on Silicon

Regrowth-Free GaN-Based Complementary Logic on a Si Substrate

Nadim Chowdhury, Qingyun Xie, Mengyang Yuan, Kai Cheng, Han Wui Then, Tomás Palacios

IEEE Electron Device Letters · 10.1109/led.2020.2987003

Monolithically integrated n- and p-channel GaN transistors on a single heterostructure, with no regrowth step required
Demonstrated a complementary inverter with a record voltage gain of ~27 V/V
Maintained clean switching characteristics up to 300 °C, proving suitability for high-temperature logic

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Epitaxial structure, TEM image, and fabricated inverter chip for the regrowth-free GaN complementary logic platform.

Conference

The First Self-Aligned GaN p-FET: A Building Block for Complementary GaN

First Demonstration of a Self-Aligned GaN p-FET

Nadim Chowdhury, Qingyun Xie, Mengyang Yuan, Nitul S. Rajput, Xiang Peng, Kai Cheng, Han Wui Then, Tomás Palacios

IEDM · 10.1109/iedm19573.2019.8993569

Demonstrated a self-aligned GaN p-FET process with a 100 nm channel length
Achieved a record ON-resistance of 400 Ω·mm and ON-current above 5 mA/mm — best-in-class for GaN p-FETs at the time
Co-integrated with an n-channel p-GaN-gated transistor, validating complementary logic via compact modeling and inverter simulation

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STEM image and schematic of the self-aligned GaN p-FET with a 100 nm channel length.

Journal

A Milestone for GaN CMOS: The First High-Performance p-Channel FinFET

Self-Aligned E-Mode GaN p-Channel FinFET With ION > 100 mA/mm and ION/IOFF > 10⁷

Nadim Chowdhury, Qingyun Xie, Tomás Palacios

IEEE Electron Device Letters · 10.1109/led.2022.3140281

Demonstrated a self-aligned GaN p-FinFET with I_ON ≈ 140 mA/mm and I_ON/I_OFF > 10⁷ — a record for GaN p-channel devices
The FinFET geometry compensates for GaN's inherently low hole mobility (~20 cm²/V·s) through superior electrostatic control
Achieved enhancement-mode operation with a record-low subthreshold swing of 80 mV/dec

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SEM cross-section of the fabricated self-aligned GaN p-channel FinFET.

Conference

Scaling Down GaN p-MOSFETs: The Physics Behind Better Performance

Field-induced Acceptor Ionization in Enhancement-mode GaN p-MOSFETs

Nadim Chowdhury, Qingyun Xie, John Niroula, Nitul S. Rajput, Kai Cheng, Han Wui Then, Tomás Palacios

IEDM · 10.1109/iedm13553.2020.9371963

Fabricated GaN p-MOSFETs with channel lengths scaled down to 200 nm
Uncovered field-induced acceptor ionization as the key mechanism boosting drive current at short channel lengths
Achieved a record combination of 45 mA/mm ON-current and a 10⁴ ON-OFF ratio among p-channel GaN devices

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Contact and sheet resistance vs. bias, and 3D schematic of the self-aligned GaN p-MOSFET gate stack.

Journal

Cracking the Contact Problem: Fermi-Level Pinning on p-Type GaN

Barrier heights and Fermi level pinning in metal contacts on p-type GaN

Sumaiya Wahid, Nadim Chowdhury, Md. Kawsar Alam, Tomás Palacios

Applied Physics Letters · 10.1063/5.0010699

Benchmarked five metal contacts (Ni, Ir, Ru, Mo, W/Au) on p-GaN using a single, uniform epitaxial platform
Found strong Fermi-level pinning across all metals (pinning factor ~0.15), explaining persistently high contact resistance
Identified Ru/Au as the standout performer, with an ultra-low contact resistivity of 3.45 × 10⁻⁶ Ω·cm²

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Current–voltage characteristics of five bilayer metal contacts on p-GaN used to extract Fermi-level pinning and contact resistivity.

Journal

A New Gate Architecture for Linear GaN Power Amplifiers

AlGaN/GaN-Based Multimetal Gated High-Electron-Mobility Transistor With Improved Linearity

Md. Tasnim Azad, Toiyob Hossain, Bejoy Sikder, Qingyun Xie, Mengyang Yuan, Eiji Yagyu, Koon Hoo Teo, Tomás Palacios, Nadim Chowdhury

IEEE Transactions on Electron Devices · 10.1109/ted.2023.3311422

Proposed the multimetal gate (MMG) concept — spatially varying the gate work function along the device width
TCAD-calibrated simulations show 6.3 dB higher OIP3/Pdc and 12.9 dB lower IMD3 versus a baseline HEMT
Delivered simultaneous gains in linearity, output power (6.91 W/mm), and efficiency (65% PAE)

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3D schematic of the multimetal-gated AlGaN/GaN HEMT with key structural parameters for improved linearity.

Journal

Beyond Room Temperature: Hole Transport Physics in p-GaN Heterostructures

Hole transport mechanism at high temperatures in p-GaN/AlGaN/GaN heterostructure

Bejoy Sikder, Toiyob Hossain, Qingyun Xie, John Niroula, Nitul S. Rajput, Koon Hoo Teo, Hiroshi Amano, Tomás Palacios, Nadim Chowdhury

Applied Physics Letters · 10.1063/5.0203344

Combined Schottky-emission and space-charge-limited-current (SCLC) models to explain p-GaN conduction across bias and temperature
Pinpointed trap states in the p-GaN channel as a key factor governing high-temperature current transport
Provided design insight for GaN electronics destined for harsh environments — from downhole drilling to planetary probes

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TEM cross-section of the Ru/p-GaN contact after annealing at 500 °C, showing the metal–semiconductor interface at increasing magnification.

Journal

Engineering Linearity: Multimetal Gates for Cleaner 5G Power Amplifiers

System-Technology Co-Optimization of Multimetal Gated AlGaN/GaN HEMT for Improved RF Linearity

Toiyob Hossain, Tanvir Hossain, AKM Anindya Alam, Bejoy Sikder, Qingyun Xie, Mengyang Yuan, Eiji Yagyu, Koon Hoo Teo, Tomás Palacios, Nadim Chowdhury

IEEE Journal of the Electron Devices Society · 10.1109/jeds.2024.3506618

Achieved a 10.7 dB improvement in OIP3/PDC by using a multimetal gate scheme to suppress third-order transconductance (gm3)
Delivered a 6× higher 1-dB compression point (3.60 vs. 0.60 W/mm) compared to a conventional HEMT
Validated under real 5G FR1 signal conditions — ACPR held below –40 dBc with a 2.6% reduction in EVM

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Multimetal gate schematic and ACPR/EVM performance of the MMG HEMT under 16- and 64-QAM 5G FR1 signals.

Journal

Machine Learning Meets GaN: Inverse-Designing RF Power Transistors

Inverse Design of AlGaN/GaN HEMT RF Device with Source Connected Field Plate

A Das, Saimur Rahman Arnab, Xiaofeng Xiang, Rafid Hassan Palash, Toiyob Hossain, Bejoy Sikder, Eiji Yagyu, Marika Nakamura, Koon Hoo Teo, Nadim Chowdhury

Advanced Theory and Simulations · 10.1002/adts.202401207

Built an ANN model (R² = 99%, <1% error) that predicts HEMT structural parameters directly from target breakdown voltage and leakage specs
Coupled the ANN with a genetic algorithm to identify Pareto-optimal field-plate designs, validated against TCAD (1.67% error)
Introduced a fast, field-based method to predict current collapse — bypassing slow pulsed-DC characterization

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Simulated electric-field maps across field-plate variations and the ANN architecture used for inverse design of the AlGaN/GaN HEMT.

Conference

Fine-Tuning Light-Activated GaN Transistors for Faster, Cleaner Switching

Performance Optimization of GaN Based Optically Triggered Transistors

Rafid Hassan Palash, Toiyob Hossain, Bejoy Sikder, Qingyun Xie, Victor Moroz, Tomás Palacios, Nadim Chowdhury

IEDM · 10.1109/iedm50854.2024.10873587

Built the first experimentally calibrated TCAD models explaining optically triggered (OT) GaN transistor physics
Optimized barrier thickness, Al composition, and back-barrier design to achieve an 8× faster response time
Extended the optimization to a vertical GaN FinFET, boosting ON-OFF ratio while suppressing persistent photocurrent

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Fabricated device layout, epitaxial structure, TCAD calibration workflow, and measured vs. simulated I–V and transient response of the optically triggered GaN transistor.

Journal

Decoding Hole Traps in p-GaN: A Path to Better GaN CMOS

Role of Mg hole traps in hole transport of p-GaN/UID-GaN/AlGaN/GaN heterostructure

Tanvir Hossain, A. K. M. Anindya Alam, Qingyun Xie, Hiroshi Amano, Tomás Palacios, Nadim Chowdhury

Applied Physics Letters · 10.1063/5.0333494

Identified Mg-related hole traps (110 meV activation energy) as the dominant factor limiting hole transport in bulk p-GaN
Showed that sheet resistance follows a Poole–Frenkel field dependence, explaining why conduction changes with bias
Revealed Schottky barrier lowering via thermionic field emission at the Ru/p-GaN contact — a key input for contact design

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Epitaxial schematic of the p-GaN/UID-GaN/AlGaN/GaN heterostructure with Ru source and drain contacts used for temperature-dependent hole transport analysis.

Conference

Switching GaN with Light: A New Gate Stack for Optical Triggering

Gate Stack Engineering and Carrier Dynamics of Optically Triggered GaN Transistors on 650V GaN-on-Si Power Platform

Rafid Hassan Palash, Jung-Han Hsia, Soumik Saha, Nittya Ananda Biswas, Qingyun Xie, Victor Moroz, Tomás Palacios, Nadim Chowdhury

IEDM · 10.1109/IEDM50572.2025.11353658

Enabled optical triggering at longer wavelengths (≥395 nm) for the first time, overcoming the limits of conventional UV-triggered GaN switches
Proposed a novel p-InGaN/p-GaN/AlGaN/GaN gate stack, reaching a responsivity of 6.7 × 10³ A/W
Cut fall time by 5.75× relative to conventional optically triggered transistor designs

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Device schematics and TCAD calibration of the lateral p-GaN gate optically triggered HEMT, showing measured vs. simulated I–V, intensity, and transient response.